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I. Course Introduction:
In June 2015, Intel announced the acquisition of Altera, the world's second largest FPGA vendor, for $ 16.7 billion. FPGAs helped deep learning make Google's Alpha Dog defeat the human Go champion, and FPGA ushered in new development opportunities. Modern FPGA design drives innovation for engineers, but the increase in system complexity presents new challenges for FPGA designers. In the face of more and more complex FPGA systems, engineers need a more reasonable design and verification method; meanwhile, the increasingly large design also puts forward new requirements for timing optimization. These have become the core issues of modern FPGA design. At the same time, as FPGAs start to play an increasingly important role in the entire system, the interface technology of FPGAs, the interface technology with external processors, functional chips and even other systems, and the design of FPGA embedded systems have also become FPGAs. Design new points and difficulties.
This course is three days long. By setting up "Advanced Features and Tools for Altera Devices", "FPGA Data Dominated System Design and Verification", "FPGA Control Dominated System Design", "FPGA Advanced Interface and System Co-Design" , "FPGA timing analysis, constraints and optimization", "FPGA embedded system development" six major topics, and strive to help students better understand the FPGA design method, better solve practical problems encountered in work and scientific research.
Signal Processing Expert Committee of China High-Tech Industrialization Research Association
Beijing Zhongji Saiwei Cultural Development Co., Ltd.
Beijing Zhongji Roewe Technology Co., Ltd.
2017年4月21-23日(20日报到) 3. Training time: April 21-23, 2017 (Report on the 20th)
北 京（具体地点及路线图详见报到通知） 4. Training location: Beijing (for specific locations and route maps, please refer to the registration notice)
V. Training objects:
The course is suitable for engineers, teachers and other engineering and technical personnel who use Altera FPGA devices for scientific research, teaching and product development, as well as graduate students and senior undergraduates in related professional fields.
The tools used are Quartus Prime and Modelsim, and the hardware is the Cyclone V DE1SOC hardware development platform.
Session 1: Advanced Features and Tools for Altera Devices
If a workman wants to be good, he must first sharpen his weapon. In order to be able to complete a reasonable FPGA design, it is necessary to have a deep understanding of the characteristics and design methods of the FPGA device itself, and to deepen the scientific design process of FPGA design in this section. The main contents are as follows:
Altera device advanced features and applications:
√ Altera latest device structure
√ On-chip memory
√ Digital signal processing unit
√ LogicLock design method
√ Clock management
√ High-speed serial transceivers, etc.
√ Advanced use of Quartus II / Quartus Prime tools
√ Incremental compilation method, etc.
Altera FPGA design method and flow:
√ Standard scientific design flow of Altera FPGA
√ Pre- and post-FPGA simulation with Modelsim
√ How to design FPGA based on performance requirements, including interface definition, resource evaluation, etc.
Session 2: FPGA Data Dominated System Design and Verification
FPGA is used to meet the increasingly complex system design with its highly customized and parallel features. Applications of FPGAs in cutting-edge technology fields are everywhere, such as the application of digital signal processing and special algorithms, video codec systems, etc. However, complex FPGA system design requires us to establish a more effective design and verification method. This topic will discuss the above issues from two aspects of data dominant and control dominant systems.
√ FPGA design principles: retiming, pipeline, parallel structure, ping pong structure, etc.
√ FPGA simulation and design verification skills, including testbench design that can synthesize RTL design and FPGA
√ FPGA basic logic and algorithm realization basic structure: data path and control unit
√ Data dominant system design and example analysis (CORDIC, FIR, FFT, channel codec, etc.) represented by digital signal processing technology
Session 3: FPGA Control Dominates System Design
This topic introduces the logic design method based on ASM and ASMD. This design method greatly simplifies the design of state machines and is widely used in algorithmic state machines. At the same time, by explaining the design of the pipeline, students will understand how to optimize the state machine through standardized processes and analysis.
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√ ASM-based state machine design and ASMD-based algorithm state machine design
√ Process and method of finite state machine design
√ Division and optimization of pipeline
√ Control dominant system design and example analysis (SPI interface, I2C, UART, etc.)
Session 4: FPGA Advanced Interface and System Co-design
An important task of FPGA is to interface with various analog and digital peripherals. FPGA provides the implementation of almost all interfaces in the industry. Interface design is often one of the biggest challenges in FPGA design. At the same time, the design of the interface between FPGA and DSP processor or external controllers such as USB, Ethernet and other chips is also an issue of increasing concern in system-level design. Especially the integrated design with DSP has become a special subject in FPGA design.
√ High-speed parallel interface and cache design
√ High-speed differential interface and high-speed serial transceiver design
√ FPGA Ethernet Interface Example
√ FPGA HPS interface design
Session 5: FPGA Timing Analysis, Constraints and Optimization
"Good sequential circuits are not simulated, but are constrained by RTL design and timing constraints." Timing analysis and constraints are an essential part of designing FPGA high-speed processing systems. This topic discusses timing constraint design through the Quartus design tool, and explains asynchronous clock domain signal processing techniques. Through the explanation of the entire timing optimization process, it helps students to establish a complete timing design and optimization concept.
√ Basics of static timing analysis: including setup time, hold time, clock skew, Recovery and Removal, etc.
√ Asynchronous clock domain signal processing technology: slow clock domain signals enter the fast clock domain, fast clock domain signals enter the slow clock domain
√ Timing problems and solutions in FPGA
√ Use Quartus tools to design timing constraints: including input timing constraints, register-to-register timing constraints, output timing constraints, etc.
√ Design example analysis: processing method of asynchronous clock domain signal
√ Design example analysis: how to use the QuartusII timing analysis tool to perform timing constraints to speed up the pipeline
√ Analysis of design examples: When the timing does not meet the requirements, how to optimize the timing to achieve the design goal
Session 6: FPGA Embedded System Development
FPGA technology is becoming more and more complex, and the development of the system becomes more and more time-consuming. And more and more system requirements put forward extremely high requirements for system integration. Altera further proposes the concept of Qsys on the basis of SOPC, which greatly facilitates the integration of the system, so that designers only need to focus on the design itself, interconnection and system integration are all completed automatically by the design software, which greatly improves the design efficiency. At the same time, a large number of Qsys compatible components greatly facilitate the development of users and speed up the market.
At the same time as the hardware design, the implementation of the Nios II soft core on the FPGA and the ARM Cotex-A9 processor has also greatly improved the integration of the system, freeing FPGA engineers from complex logic, and the processor completes more flexible functions The FPGA achieves high performance and high interconnectivity. You can even program FPGAs using the OpenCL framework, gaining maximum flexibility and achieving extremely high performance.
√ Altera Qsys Design
√ NIOS II soft core processor and its application
√ Altera Qsys interface design
√ Design experiments based on Qsys and NIOS II
√ FPGA SoC and OpenCL
Mr. He: He graduated from Tsinghua University with a PhD in engineering and has more than 10 years of development experience in Altera FPGAs. He has long been committed to the research and development of wireless communication systems and video communication systems, and is responsible for and participating in many large-scale FPGA development projects. He has a solid theoretical foundation, rich practical experience, and has lectured on many trainings, which has been well received by trainees.
3600元/人（含资料、午餐、课时费，学习后由主办单位颁发证书） IX. Fees: 3,600 yuan / person (including materials, lunch, and class hours, after the study, the organizer will issue a certificate)
010-64113137 X. Consulting Contact: 010-64113137